1. Technical Field
Embodiments relate to a phase-change random access memory device, a system having the same, and associated methods.
2. Description of the Related Art
FIG. 1 illustrates an equivalent circuit diagram of a unit cell of a phase-change random access memory (PRAM) device that includes a phase-change material GST. Referring to FIG. 1, the unit cell C may include a memory device ME and a P-N diode D. A bit line BL may be connected to the phase-change material GST, which may be connected to a P-junction of the diode D. A word line WL may be connected to an N-junction of the diode D. In another circuit (not shown), the PRAM device may include a transistor connected to the phase-change material GST instead of the diode D.
In the PRAM device, current supplied to the bit line BL to perform write and read operations may influence subsequent write and read operations. For example, when an operation of writing data “1” in a first cell connected to a first bit line is performed, a current is supplied to the first bit line. An undesirable voltage may sometimes be present in the first bit line even when the operation of writing data “1” is terminated. Due to this undesirable voltage, a subsequent write operation of the first cell may be inaccurately performed, or the write or read operations of the first cell may be erroneously performed during the write and read operations of another cell.
In order to solve these problems, a process of discharging bit lines connected to cells to be written to, or read from, may be performed before the write and read operations. However, as the capacity of the PRAM device is increased, the bit line may be made longer, and a parasitic resistance and a parasitic capacitance may be increased during the discharge operation. Such a phenomenon not only increases a discharge time required to perform the discharge operation, but also interferes with accurate discharge operations.